The art of schematic entry is well established. The majority of computer aided engineering work stations allow the user to enter the graphical representations for such elements as integrated circuits, resistors, capacitors and connecting lines. Then these entries are compiled in a batch mode to produce computer meaningful data such as an element connectivity list, a parts list, an error report and simulation data.
The major disadvantage of this process is that design compilation takes a long time and is proportional to the size of the schematic. Also, even the smallest design correction requires the entire schematic to be recompiled anew. This process results in schmematic capture software that is time consuming and inconvenient to use particularly when there are numerous design changes.
Another disadvantage of the present schematic capture software is that any design error shows up only after batch compilation of the schematic, which is late in the design process.
Still another disadvantage of the present methods is that the logic simulation of the schematic design can take place only after schematic batch compilation, creating a large time delay between the schematic entry or correction and observation of its effect on the system behavior.
The biggest disadvantage of the present computer aided engineering work stations is that they are labor intensive and incapable of providing fully automated timing analysis of the logic design. The work stations can only provide the mini-max analysis that calculates the zones of uncertainty in the combinatorial circuits, which are used in a great majority of logic designs. Furthermore, the present work stations cannot calculate the digital noise filtering properties of logic devices, which is mandatory to effectively model the circuit's behavior.